With reference to a drawing, the basic structure of a SRAM memory cell that is a semiconductor memory element is described below.
As shown in a circuit diagram of FIG. 22, a SRAM memory cell is composed of a flip-flop circuit that functions as an information storage section and a pair of transmission transistors T1 and T2 that control the conduction between data lines (bit lines, BL1 and BL2) which serve for writing and reading of the information and the flip-flop circuit. The flip-flop circuit is made of, for example, a pair of CMOS (Complementary Metal Oxide Semiconductor) inverters and each CMOS inverter contains a driver transistor D1 (D2) and a load transistor P1 (P2).
One side of source/drain regions in each transmission transistor T1 (T2) is connected to drains of a load transistor P1 (P2) as well as a driver transistor D1 (D2), and the other side thereof is connected to a bit line BL1 (BL2). Further, gates of a pair of the transmission transistors T1 and T2 each form a part of a word line WL and are connected with each other.
The gates of the driver transistor D1 and the load transistor P1 which constitute one of the CMOS inverters are connected to the drains (the storage node N2) of a driver transistor D2 and a load transistor P2 which constitute the other of the CMOS inverters. Further, the gates of the driver transistor D2 and the load transistor P2 which constitute the latter of the CMOS inverters are connected to the drains (the storage node N1) of the driver transistor D1 and the load transistor P1 which constitute the former of the CMOS inverters. In effect, a pair of CMOS inverters are arranged such that the input/output section of each CMOS inverters may be cross-coupled with the gate of the other CMOS inverter through one of a pair of interconnections L1 and L2, which are called the local interconnections.
Further, a reference voltage (VSS, for example, GND) is applied to the source region of each one of the driver transistors D1 and D2, and a supply voltage (VCC) is applied to the source region of each one of the load transistors P1 and P2.
The SRAM cell described above has excellent element characteristics such as the high noise tolerance and the small stand-by power. Further, for the SRAM cell of this sort, in view of element characteristics, selection of the materials and layout are carefully made so as not to lose symmetry of the element structure (in other words, to prevent imbalance from occurring) within the limits of possibility.
However, the SRAM cell described above has a problem that a cell area tends to become considerably large, due to requirements to have 6 transistors in one memory cell and isolate p-type MOSs from n-type MOSs within one and the same cell as well as the need of numerous interconnections. Another disadvantage it has is the large number of the steps in the manufacturing method thereof.
Therefore, with respect of the structure of the 6-transistors type SRAM cell and manufacturing method thereof, various propositions have been made so far.
For example, in Symp. on VLSI Tech., p. 64 (1998) by M. Inohara et al., a method of forming each one of a pair of local interconnections through the metal damascene process is disclosed. In this method, two tungsten (W) local interconnections which are damascene interconnections are formed in different layers, respectively, and thereby formation of a cross-couple is achieved. It is, therein, described that, because a tungsten plug reaching an active region on a substrate and one (a lower layer) of the local interconnections are formed by making their openings simultaneously, this SRAM memory cell can be fabricated without setting additional photomasks or increasing the number of the steps in fabrication. Nevertheless, in this method, because the other one (an upper layer) of the local interconnections should be formed in such a way that its disposition could avoid any contact with the lower layer of the local interconnections, a reduction in cell size attained cannot be sufficiently large.
Further, in Japanese Patent Application Laid-open No. 251457/1999, it is described that, in fabrication of a 6-transistors type cell, a pair of local interconnections are both formed with a metal damascene process, and besides disposed on one and the same layer. Yet, in this method, too, it is difficult to achieve a sufficient reduction in cell size, since a pair of local interconnections must be disposed so as not to come into contact with each other.
Meanwhile, in Japanese Patent Application Laid-open No. 260510/1997, with the object of reducing in size of the memory cell and improving the α-ray soft error resistance, there is disclosed an element structure described below. A similar structure is also described by F. Ootsuka et al. in IEDM, p. 205 (1998).
In this structure, a pair of local interconnections to form a cross couple are formed by applying etching to different conductive layers, respectively. An upper layer of local interconnections is disposed so as to overlap a lower layer of local interconnections, and these local interconnections separated by an insulating film (a capacity insulating film) constitute a capacitor element.
However, for such an element structure, a contact hole must be formed separately for each one of a pair of local interconnections so that a substantially large number of steps are required in its fabrication. Further, in this structure, the local interconnections are laid in a relatively wide range, extending even as far as the top of a gate electrode, with a thin insulating film lying therebetween. When a conductive film pattern is to be formed on such an uneven substrate surface, there arises a problem that superfluous parts of the conductive film may remain at unrequired positions because, in performing patterning of the conductive film by means of anisotropic etching, it is difficult to remove portions of the conductive film around stepped parts. Further, when a capacitor insulating film is to be formed on such an uneven surface, the film thickness thereof tends to increase around the stepped parts. On the other hand, if the film thickness around the stepped parts is to be made satisfactorily thin, there may arise another problem that the film thickness in the flat region becomes excessively thin, which may result in damage to insulation thereof. In short, formation of a thin and, at the same time, even capacitor insulating film is difficult to achieve.
In view of the above discussion, it would be desirable to provide a technology capable to reduce easily the memory cell size of the SRAM without unduly increasing the number of the steps in the manufacturing method thereof. It would also be desirable to provide a technology to improve the α-ray soft error resistance of the SRAM.